XC2C256-7VQG100I

Product Summary

The XC2C256-7VQG100I is an FPGA. The XC2C256-7VQG100I is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system .is improved. The XC2C256-7VQG100I consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks of the XC2C256-7VQG100I consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Parametrics

XC2C256-7VQG100I absolute maximum ratings (1)Supply voltage relative to ground: –0.5 to 2.0 V; (2)Supply voltage for output drivers: –0.5 to 4.0 V; (3)JTAG input voltage limits: –0.5 to 4.0 V; (4)JTAG input supply voltage: –0.5 to 4.0 V; (5)Input voltage relative to ground: –0.5 to 4.0 V; (6)Voltage applied to 3-state output: –0.5 to 4.0 V; (7)Storage Temperature (ambient): –65 to +150 ℃; (8)Junction Temperature: +150 ℃.

Features

XC2C256-7VQG100I features: (1)Optimized for 1.8V systems: As fast as 5.7 ns pin-to-pin delays, As low as 13 μA quiescent current; (2)Industry is best 0.18 micron CMOS CPLD:Optimized architecture for effective logic synthesis. Refer to the CoolRunnerII family data sheet for architecture description; Multi-voltage I/O operation 1.5V to 3.3V; (3)Available in multiple package options: 100-pin VQFP with 80 user I/O;144-pin TQFP with 118 user I/O; 132-ball CP (0.5mm) BGA with 106 user I/O; 208-pin PQFP with 173 user I/O; 256-ball FT (1.0mm) BGA with 184 user I/O; Pb-free available for all packages; Advanced system features: Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface; IEEE1149.1 JTAG Boundary Scan Test; Optional Schmitt-trigger input (per pin); Unsurpassed low power management,DataGATE enable (DGE) signal control; Two separate I/O banks; RealDigital 100% CMOS product term generation; Flexible clocking modes: Optional DualEDGE triggered registers, Clock divider (divide by 2,4,6,8,10,12,14,16), CoolCLOCK; Global signal options with macrocell control:Multiple global clocks with phase selection per macrocell, Multiple global output enables, Global set/reset; Advanced design security; PLA architecture: Superior pinout retention, 100% product term routability across function block; Open-drain output option for Wired-OR and LED drive; Optional bus-hold, 3-state or weak pull-up on; selected I/O pins; Optional configurable grounds on unused I/Os; Mixed I/O voltages compatible with 1.5V, 1.8V,2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility; Hot pluggable.

Diagrams